The invention relates to a DDR memory and to a storage method in such a DDR memory in accordance with the precharacterizing part of claim 1 or 4, and particularly to stabilization of write access operations.
Whereas read and write operations in normal memories take place only on the rising or falling edge of a clock signal, data in DDR (double data rate) memories are read and written both on rising edges and on falling edges of the clock signal, i.e. at double the data rate. In this case, the clock signal used for reading in the data differs from the clock signal used for transferring instructions. During write access to the memory, the data (DQ) are delivered by a controller together with a write clock signal (data strobe clock, DQS) in order to ensure a fixed temporal relationship between data and the write clock signal DQS. The write instruction is synchronized with an instruction clock CLK.
The phase of the write clock signal DQS (and hence of the data) can fluctuate relative to an external clock signal for addresses and commands (CLK), specifically to the extent of a shift forward or back through one quarter of a clock cycle. For the write part of the data path in the memory, this means that the data are not read in and synchronized with the internal clock signal derived from the external clock signal CLK, but rather with the write clock signal DQS. However, external access to the memory array, including address decoding, is derived from the respective write command WR and from an address information item ADR. The write command WR and the address information item ADR are for their part synchronized with the external clock signal CLK. The result of this is that the write path needs to contain an interface between signals which are synchronized with the write clock signal DQS and signals which are synchronized with the clock signal CLK for addresses and commands. The transition between the two synchronization domains is called a xe2x80x9cclock-domain changexe2x80x9d. Specifically, the data at the input of DDR memories are synchronized with the write clock signal DQS and are subsequently written synchronously to a memory-internal data bus in a further circuit using an external write clock signal WRCLK.
If the write clock signal DQS and the external write clock signal WRCLK do not observe particular specifications, data can be inadvertently overwritten when transferring between the DQS and CLK areas. The reliability of data transfer between the DQS and CLK areas is dependent on the maximum shift in the external write clock signal WRCLK with respect to the clock signal CLK and hence also with respect to the write clock signal DQS.
It is an object of the invention to make the transfer of data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable.
The invention achieves this object by means of the DDR memory in accordance with claim 1 and by the storage method in accordance with claim 4. Preferred embodiments of the invention are covered by the subclaims.
By introducing a pulsed interface between the DQS-synchronous and the CLK-synchronous area, the write clock signal DQS is shifted with respect to the external write clock signal WRCLK, so that relatively long intervals of time arise between the two. It is possible to double the interval. This makes time for receiving the data in the subsequent synchronization area, and data transfer becomes more reliable.
The inventive DDR memory having a plurality of memory cells which each have a prescribed word length, which comprises: a first clock signal input for receiving a system clock signal, a second clock signal input for receiving a data clock signal, an instruction input for reading in and decoding a write instruction which is synchronized with the system clock signal, a serial data input for reading in serial data on a rising edge and on a falling edge of the data clock signal, a serial-parallel converter for putting together a prescribed number of data items from the data read in to give a prescribed number of words from data words having a prescribed word length, is characterized by an interface memory which copies the at least one data word from the serial-parallel converter when it receives a copy signal which is synchronous with the data clock signal, and which outputs the at least one data word to a bus when it receives an output signal which is synchronous with the system clock signal.
In particular, the invention provides a device for producing a time window in which production of the copy signal is inhibited by the data clock.
In one preferred embodiment of the invention, the device for producing a time window comprises a counter, whose output state changes once from a first to a second output state between the reading-in of a first data value and of a last data value for the at least one data word, and a clock synchronization device which outputs the copy signal when a data clock signal is applied and the counter has the second output state.
The inventive storage method for storing data in a DDR memory, as described above, having a plurality of memory cells which each have a prescribed word length is characterized by an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronized with the data clock signal and outputting the at least one data word to a bus upon receipt of an output signal which is synchronous with the system clock signal.
One advantage of the invention is that the pulsed interface memory extends the maximum possible tolerance for production-related and operation-related fluctuations (voltage, temperature), so that demands on other circuits can be reduced.
Other features and advantages of the invention can be found in the description below of an exemplary embodiment, where reference is made to the appended drawings.